Altera Embedded Peripherals IP - Manual (Page 49)

The options provided are not intended to cover the wide range of flash devices available in the market. If
the flash chip on your target board does not appear in the Presets list, you must configure the other
settings manually.
Setting Size
The size setting specifies the size of the flash device. There are two settings:
• Address Width—The width of the flash chip's address bus.
• Data Width—The width of the flash chip's data bus
The size settings cause Qsys to allocate the correct amount of address space for this device. Qsys will
automatically generate dynamic bus sizing logic that appropriately connects the flash chip to Avalon-MM
master ports of different data widths.
Avalon Interface Specifications
For details about dynamic bus sizing, refer to the Avalon Interface Specifications.
Timing page
The options on this page specify the timing requirements for read and write transfers with the flash
device.
Refer to the specifications provided with the common flash device you are using to obtain the timing
values you need to calculate the values of the parameters on the Timing page.
The settings available on the Timing page are:
• Setup—After asserting chipselect, the time required before asserting the read or write signals. You can
determine the value of this parameter by using the following formula:
Setup = tCE (chip enable to output delay) - tOE (output enable to output delay)
• Wait—The time required for the read or write signal to be asserted for each transfer. Use the following
guideline to determine an appropriate value for this parameter:
The sum of Setup, Wait, and board delay must be greater than tACC, where:
• Board delay is determined by the TCO on the FPGA address pins, TSU on the device data pins, and
propagation delay on the board traces in both directions.
• tACC is the address to output delay.
• Hold—After deasserting the write signal, the time required before deasserting the chipselect signal.
• Units—The timing units used for the Setup, Wait, and Hold values. Possible values include ns, μs, ms,
and clock cycles.
Avalon Interface Specifications
For more information about signal timing for the Avalon-MM interface, refer to the Avalon Interface
Specifications.
Software Programming Model
This section describes the software programming model for the CFI controller. In general, any Avalon-
MM master in the system can read the flash chip directly as a memory device. For Nios II processor users,
Altera provides HAL system library drivers that enable you to erase and write the flash memory using the
HAL API functions.
UG-01085
2014.24.07
Setting Size 5-3
Common Flash Interface Controller Core Altera Corporation
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