Altera Embedded Peripherals IP - Manual (Page 274)

This block contains the majority of the VIC CSRs. The CSRs are accessed via the Avalon-MM slave
interface.
Optional output from another VIC core can also come into the interrupt request block. Refer to the Daisy
Chaining VIC Cores section for more information.
Each interrupt can be driven either by its associated
irq_input
signal (connected to a component with an
interrupt source) or by a software trigger controlled by a CSR (even when there is no interrupt source
connected to the
irq_input
signal).
Figure 28-3: Interrupt Request Block
irq_inpu t
(external interrupt input)
INT_RAW_STATUS INT_ENABLE INT_PENDING
SW_INTER RUPT
RIL
per port
PortId[5:0]
x32
RRS[5:0]
x32
RNMI
x32
RIL[5:0]
x32
RRS
per port
RNMI
per port
Priority Processing Block
The priority processing block chooses the interrupt with the highest priority. The block receives informa‐
tion for each interrupt from the interrupt request block and passes information for the highest priority
interrupt to the vector generation block.
The interrupt request with the numerically-largest RIL has priority. If multiple interrupts are pending
with the same numerically-largest RIL, the numerically-lowest IRQ index of those interrupts has priority.
The RIL is a programmable interrupt level per port. An RIL value of zero disables the interrupt. You
configure the bit width of the RIL when you create the component. Refer to the Parameters section for
configuration options.
Vector Generation Block
The vector generation block receives information for the highest priority interrupt from the priority
processing block. The vector generation block uses the port identifier passed from the priority processing
block along with the vector base address and bytes per vector programmed in the CSRs during software
initialization to compute the RHA.
Table 28-4: RHA Calculation
RHA = (port identifier x bytes per vector) + vector base address
The information then passes out of the vector generation block and the VIC using the Avalon-ST
interface. Refer to the VIC Avalon-ST Interface Fields table for details about the outgoing information.
The output from the VIC typically connects to a processor or another VIC, depending on the design.
UG-01085
2014.24.07
Functional Blocks 28-5
Vectored Interrupt Controller Core Altera Corporation
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