Altera Embedded Peripherals IP - Manual (Page 62)

characters via a console, giving the appearance of a terminal session with the system executing in
hardware. The following options are available:
• Do not generate ModelSim aliases for interactive windows—This option does not create any
ModelSim macros for character I/O.
• Create ModelSim alias to open a window showing output as ASCII text—This option creates a
ModelSim macro to open a console window that displays output from the write FIFO. Values written
to the write FIFO via the Avalon interface are displayed in the console as ASCII characters.
• Create ModelSim alias to open an interactive stimulus/response window—This option creates a
ModelSim macro to open a console window that allows input and output interaction with the core.
Values written to the write FIFO via the Avalon interface are displayed in the console as ASCII
characters. Characters typed into the console are fed into the read FIFO, and can be read via the
Avalon interface. When this option is enabled, the simulated character input stream option is ignored.
Hardware Simulation Considerations
The simulation features were created for easy simulation of Nios II processor systems when using the
ModelSim simulator. The simulation model is implemented in the JTAG UART core's top-level HDL file.
The synthesizable HDL and the simulation HDL are implemented in the same file. Some simulation
features are implemented using
translate on/off
synthesis directives that make certain sections of
HDL code visible only to the synthesis tool.
AN 351: Simulating Nios II Processor Designs
For complete details about simulating the JTAG UART core in Nios II systems, refer to AN351:
Simulating Nios II Processor Designs.
Other simulators can be used, but require user effort to create a custom simulation process. You can use
the auto-generated ModelSim scripts as references to create similar functionality for other simulators.
Note: Do not edit the simulation directives if you are using Altera’s recommended simulation
procedures. If you change the simulation directives to create a custom simulation flow, be aware
that Qsys overwrites existing files during system generation. Take precautions to ensure your
changes are not overwritten.
Software Programming Model
The following sections describe the software programming model for the JTAG UART core, including the
register map and software declarations to access the hardware. For Nios II processor users, Altera
provides HAL system library drivers that enable you to access the JTAG UART using the ANSI C
standard library functions, such as
printf()
and
getchar()
.
HAL System Library Support
The Altera-provided driver implements a HAL character-mode device driver that integrates into the HAL
system library for Nios II systems. HAL users should access the JTAG UART via the familiar HAL API
and the ANSI C standard library, rather than accessing the JTAG UART registers.
ioctl()
requests are
defined that allow HAL users to control the hardware-dependent aspects of the JTAG UART.
Note: If your program uses the Altera-provided HAL device driver to access the JTAG UART hardware,
accessing the device registers directly will interfere with the correct behavior of the driver.
UG-01085
2014.24.07
Hardware Simulation Considerations 7-5
JTAG UART Core Altera Corporation
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