Altera Embedded Peripherals IP - Manual (Page 250)

The intervanl timer core has two user-visible features:
• The Avalon Memory-Mapped (Avalon-MM) interface that provides access to six 16-bit registers
• An optional pulse output that can be used as a periodic pulse generator
All registers are 16-bits wide, making the core compatible with both 16-bit and 32-bit processors.
Certain registers only exist in hardware for a given configuration. For example, if the core is
configured with a fixed period, the period registers do not exist in hardware.
The following sequence describes the basic behavior of the interval timer core:
• An Avalon-MM master peripheral, such as a Nios II processor, writes the core's
control
register to
perform the following tasks:
• Start and stop the timer
• Enable/disable the IRQ
• Specify count-down once or continuous count-down mode
• A processor reads the
status
register for information about current timer activity.
• A processor can specify the timer period by writing a value to the period registers.
• An internal counter counts down to zero, and whenever it reaches zero, it is immediately reloaded
from the period registers.
• A processor can read the current counter value by first writing to one of the snap registers to request a
coherent snapshot of the counter, and then reading the snap registers for the full value.
• When the count reaches zero, one or more of the following events are triggered:
• If IRQs are enabled, an IRQ is generated.
• The optional pulse-generator output is asserted for one clock period.
• The optional watchdog output resets the system.
Avalon-MM Slave Interface
The interval timer core implements a simple Avalon-MM slave interface to provide access to the register
file. The Avalon-MM slave port uses the
resetrequest
signal to implement watchdog timer behavior.
This signal is a non-maskable reset signal, and it drives the reset input of all Avalon-MM peripherals.
When the
resetrequest
signal is asserted, it forces any processor connected to the system to reboot. For
more information, refer to Configuring the Timer as a Watchdog Timer.
Configuration
This section describes the options available in the MegaWizard Interace.
Timeout Period
The Timeout Period setting determines the initial value of the period registers. When the Writeable
period option is on, a processor can change the value of the period by writing to the period registers.
When the Writeable period option is off, the period is fixed and cannot be updated at runtime. See the
Hardware Options section for information on register options.
The Timeout Period is an integer multiple of the Timer Frequency. The Timer Frequency is fixed at the
frequency setting of the system clock associated with the timer. The Timeout Period setting can be
specified in units of µs (microseconds), ms (milliseconds), seconds , or clocks (number of cycles of the
system clock associated with the timer). The actual period depends on the frequency of the system clock
associated with the timer. If the period is specified in µs, ms, or seconds, the true period will be the
smallest number of clock cycles that is greater or equal to the specified Timeout Period value. For
25-2 Avalon-MM Slave Interface
UG-01085
2014.24.07
Altera Corporation Interval Timer Core
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