Pll cores, Core overview, Pll cores -1 – Altera Embedded Peripherals IP User Manual
Page 312: Core overview -1
PLL Cores
32
2014.24.07
UG-01085
Core Overview
The PLL cores, Avalon ALTPLL and PLL, provide a means of accessing the dedicated on-chip PLL
circuitry in the Altera
®
Stratix
®
, except Stratix V, and Cyclone
®
series FPGAs. Both cores are a component
wrapper around the Altera ALTPLL megafunction.
The PLL core is scheduled for product obsolescence and discontinued support. Therefore, Altera
recommends that you use the Avalon ALTPLL core in your designs.
The core takes an SOPC Builder system clock as its input and generates PLL output clocks locked to that
reference clock.
The PLL cores support the following features:
• All PLL features provided by Altera's ALTPLL megafunction. The exact feature set depends on the
device family.
• Access to status and control signals via Avalon Memory-Mapped (Avalon-MM) registers or top-level
signals on the SOPC Builder system module.
• Dynamic phase reconfiguration in Stratix III and Stratix IV device families.
The PLL output clocks are made available in two ways:
• As sources to system-wide clocks in your SOPC Builder system.
• As output signals on your SOPC Builder system module.
.
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