Altera Embedded Peripherals IP - Manual (Page 20)

Performance Considerations
Under optimal conditions, the SDRAM controller core’s bandwidth approaches one word per clock cycle.
However, because of the overhead associated with refreshing the SDRAM, it is impossible to reach one
word per clock cycle. Other factors affect the core’s performance, as described in the following sections.
Open Row Management
SDRAM chips are arranged as multiple banks of memory, in which each bank is capable of independent
open-row address management. The SDRAM controller core takes advantage of open-row management
for a single bank. Continuous reads or writes within the same row and bank operate at rates approaching
one word per clock. Applications that frequently access different destination banks require extra
management cycles to open and close rows.
Sharing Data and Address Pins
When the controller shares pins with other tri-state devices, average access time usually increases and
bandwidth decreases. When access to the tri-state bridge is granted to other devices, the SDRAM incurs
overhead to open and close rows. Furthermore, the SDRAM controller has to wait several clock cycles
before it is granted access again.
To maximize bandwidth, the SDRAM controller automatically maintains control of the tri-state bridge as
long as back-to-back read or write transactions continue within the same row and bank.
This behavior may degrade the average access time for other devices sharing the Avalon-MM tri-state
bridge.
The SDRAM controller closes an open row whenever there is a break in back-to-back transactions, or
whenever a refresh transaction is required. As a result:
• The controller cannot permanently block access to other devices sharing the tri-state bridge.
• The controller is guaranteed not to violate the SDRAM’s row open time limit.
Hardware Design and Target Device
The target device affects the maximum achievable clock frequency of a hardware design. Certain device
families achieve higher f
MAX
performance than other families. Furthermore, within a device family, faster
speed grades achieve higher performance. The SDRAM controller core can achieve 100 MHz in Altera’s
high-performance device families, such as Stratix ® series. However, the core might not achieve 100 MHz
performance in all Altera device families.
The f
MAX
performance also depends on the system design. The SDRAM controller clock can also drive
other logic in the system module, which might affect the maximum achievable frequency. For the SDRAM
controller core to achieve f
MAX
performance of 100 MHz, all components driven by the same clock must
be designed for a 100 MHz clock rate, and timing analysis in the Quartus II software must verify that the
overall hardware design is capable of 100 MHz operation.
Configuration
The SDRAM controller MegaWizard has two pages: Memory Profile and Timing. This section describes
the options available on each page.
The Presets list offers several pre-defined SDRAM configurations as a convenience. If the SDRAM
subsystem on the target board matches one of the preset configurations, you can configure the SDRAM
2-4 Performance Considerations
UG-01085
2014.24.07
Altera Corporation SDRAM Controller Core
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