Avalon-st multi-channel shared memory fifo core, Core overview, Performance and resource utilization – Altera Embedded Peripherals IP User Manual
Page 174: Avalon-st multi-channel shared memory fifo core -1, Core overview -1, Performance and resource utilization -1, The avalon
Avalon-ST Multi-Channel Shared Memory FIFO
Core
17
2014.24.07
UG-01085
Core Overview
The Avalon
®
Streaming (Avalon-ST) Multi-Channel Shared Memory FIFO core is a FIFO buffer with
Avalon-ST data interfaces. The core, which supports up to 16 channels, is a contiguous memory space
with dedicated segments of memory allocated for each channel. Data is delivered to the output interface in
the same order it was received on the input interface for a given channel.
The example below shows an example of how the core is used in a system. In this example, the core is
used to buffer data going into and coming from a four-port Triple Speed Ethernet MegaCore function. A
processor, if used, can request data for a particular channel to be delivered to the Triple Speed Ethernet
MegaCore function.
Figure 17-1: Multi-Channel Shared Memory FIFO in a System—An Example
a
F t
c
e
n
n
o
cr
et
nI
m
et
s
y
S
b
cir
Rest of the
System
Altera
FPGA
M
u
x
Port 0
Port 1
Port 2
Port 3
Channel 0
Channel 1
Channel 2
Channel 3
Processor/
Scheduler
Multi-port
Triple Speed Ethe
rnet
Multi-Channel
Shared Memory FIFO
(Receive FIFO buffer)
From
Network
Dem
u
x
Performance and Resource Utilization
This section lists the resource utilization and performance data for various Altera device families. The
estimates are obtained by compiling the core using the Quartus
®
II software.
The table below shows the resource utilization and performance data for a Stratix II GX device
(EP2SGX130GF1508I4).
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