Document revision history, Document revision history -9 – Altera Embedded Peripherals IP User Manual
Page 328

Parameter Name
Description
Default value
Allowable range
DATA_ENTRY_
DEPTH
This parameter affects
the depth of FIFO
implemented at each
data word address. The
PCI specification
allows each MSI
capable function to
support multiple
vectors up to 32. This
means a function may
allow sending MSI to a
system-specified
address (same targeted
address) with modified
system-specified data
value, up to 32 variants.
This parameter is
applied across all
message data locations
enabled in this
component. For
example: if DATA_
ENTRY_DEPTH is set
to 32, each message
data word location
contains a buffer of 32
in depth to store
incoming write values.
1
32:1
Document Revision History
Table 33-11: Document Revision History
Date and
Document
Version
Changes Made
Summary of Changes
July 2014
v14.0
-
Initial Release
UG-01085
2014.24.07
Document Revision History
33-9
Altera MSI to GIC Generator
Altera Corporation
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
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- FFT MegaCore Function (50 pages)
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- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
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- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
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