Uart device structure – Altera Embedded Peripherals IP User Manual
Page 100

Include:
Parameters:
context – device of the UART
Returns:
none
Description:
Interrupt handler to process UART interrupts to
process receiver/transmit interrupts.
Table 9-19: alt_16550_uart_rxirq
Prototype:
static void altera_16550_uart_rxirq (altera_16550_
uart_dev* dev, alt_u32
Include:
Parameters:
context – device of the UART
Returns:
none
Description:
Process a receive interrupt. It transfers the incoming
character into the receiver circular buffer, and sets
the appropriate flags to indicate that there is data
ready to be processed.
Table 9-20: alt_16550_uart_txirq
Prototype:
static void altera_16550_uart_txirq (altera_16550_
uart_dev* dev, alt_u32 status
Include:
Parameters:
context – device of the UART
Returns:
none
Description:
Process a transmit interrupt. It transfers data from
the transmit buffer to the device, and sets the
appropriate flags to indicate that there is data ready
to be processed.
UART Device Structure
9-14
UART Device Structure
UG-01085
2014.24.07
Altera Corporation
16550 UART
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)