Operation, Operation -2 – Altera Embedded Peripherals IP User Manual
Page 189
Feature
Property
Data Width
Data width = 8 bits; Bits per symbol = 8.
Channel
Not supported.
Error
Not used.
Packet
Supported.
The Avalon-MM master interface supports read and write transactions. The data width is set to 32 bits
and burst transactions are not supported.
Operation
The Avalon Packets to Transactions Converter core receives streams of packets on its Avalon-ST sink
interface and initiates Avalon-MM transactions. Upon receiving transaction responses from Avalon-MM
slaves, the core transforms the responses to packets and returns them to the requesting components via its
Avalon-ST source interface. The core does not report Avalon-ST errors.
Packet Formats
The core expects incoming data streams to be in the format shown in the table below. A response packet is
returned for every write transaction. The core also returns a response packet if a no transaction (0x7f) is
received. An invalid transaction code is regarded as a no transaction. For read transactions, the core
simply returns the data read.
Table 20-2: Packet Formats
Byte
Field
Description
Transaction Packet Format
0
Transaction code
Type of transaction. See Properties of Avalon-ST Interfaces
table.
1
Reserved
Reserved for future use.
[3:2]
Size
Transaction size in bytes. For write transactions, the size
indicates the size of the
data
field. For read transactions, the
size indicates the total number of bytes to read.
[7:4]
Address
32-bit address for the transaction.
[n:8]
Data
Transaction data; data to be written for write transactions.
Response Packet Format
0
Transaction code
The transaction code with the most significant bit inversed.
1
Reserved
Reserved for future use.
[4:2]
Size
Total number of bytes read/written successfully.
Supported Transactions
The table below lists the Avalon-MM transactions supported by the core.
20-2
Operation
UG-01085
2014.24.07
Altera Corporation
Avalon Packets to Transactions Converter Core