Yaskawa SGDB - Manual (Page 85)

3.2 Setting Parameters According to Host Controller
73
Cn-02 Bit A
Error Counter Clear Signal
Selection
Factory
Setting: 0
For Position Control Only
Selects the pulse form of error counter clear signal CLR (1CN-15).
Setting Meaning
0
Clears the error counter when the CLR
signal is set at high level. Error pulses
do not accumulate while the signal
remains at high level.
Cleared state 1CN-15
1
Clears the error counter only once when
the rising edge of the CLR signal rises.
Cleared only once at this point
1CN-15
3.2.3 Using Encoder Outputs
Encoder output signals divided inside the SERVOPACK can be output externally. These
signals can be used to form a position control loop in the host controller.
SGMj
servomotor
encoder
SGDB
SERVOPACK
Frequency
dividing
circuit
Host
controller
This output is
explained here.
Phase A
Phase B
Phase C
Phase A
Phase B
Phase C
TERMS
Divided (or dividing)
“Dividing” means converting an input pulse train from the encoder mounted on the motor
according to the preset pulse density and outputting the converted pulse. The unit is pulses
per revolution.
3