Zilog EZ80F916 - Manual (Page 94)

eZ80
®
CPU
User Manual
UM007715-0415 CPU Instruction Set
85
ADC HL, rr
ADD with Carry
Operation
HL  HL+rr+C
Description
The rr operand is any of the multibyte registers BC, DE, or HL. The rr operand and the
Carry Flag (C in the F register) are added to the contents of the HL register. The result is
stored in the HL register.
Condition Bits Affected
Attributes
kk
identifies the BC, DE, or HL register and is assembled into one of the opcodes in
Table 39 .
S
Set if result is negative; reset otherwise.
Z
Set if result is 0; reset otherwise.
H
Set if carry from bit 11; reset otherwise.
P/V
Set if overflow; reset otherwise.
N
Reset.
C
Set if carry from MSB; reset otherwise.
Mnemonic Operand ADL Mode Cycle Opcode (hex)
ADC
HL,ss X 2
ED, kk
ADC.S
HL,ss 1 3
52, ED, kk
ADC
.L HL,ss 0 3
49, ED, kk