Ld a, (mmn), Operation, Description – Zilog EZ80F916 User Manual
Page 201: Condition bits affected, Attributes
eZ80
®
CPU
User Manual
UM007715-0415
CPU Instruction Set
192
LD A, (Mmn)
Load Accumulator
Operation
A (Mmn)
Description
The CPU writes the contents of the specified memory location, Mmn, to the accumulator,
A.
Condition Bits Affected
None.
Attributes
Zilog recommends against using the .SIL and .LIS suffixes with this instruction. The .SIL
instruction fetches a 24-bit value, Mmn. However, this instruction ignores the upper byte
and uses address {MBASE, mm, nn} instead. The .LIS instruction fetches a 16-bit value,
mn. However, the .LIS instruction does not use the MBASE value. Instead, it uses address
{00, mm, nn}.
Mnemonic Operand
ADL Mode Cycle
Opcode (hex)
LD
A,(mn)
0
4
3A, nn, mm
LD
A,(Mmn)
1
5
3A, nn, mm, MM
LD.LIL
A,(Mmn)
0
6
5B, 3A, nn, mm, MM
LD.SIS
A,(mn)
1
5
40, 3A, nn, mm
Note: