Zilog EZ80F916 - Manual (Page 307)

eZ80
®
CPU
User Manual
UM007715-0415 CPU Instruction Set
298
Condition Bits Affected
None.
Attributes
0 . L The MADL control bit must be set to 1 to enable mixed-
ADL mode interrupts. The starting Program Counter is
{MBASE, PC[15:0]}. Pop a byte from SPL into ADL to
set the new memory mode (03h = ADL, 02h = Z80).
If ADL mode {
Pop the upper byte of the return address from SPL into
PC[23:16]. Pop 2 LS bytes of the return address from
{MBASE, SPS} into PC[15:0]. The ending Program
Counter is PC[23:0]
}
else Z80 mode {
Pop a 2-byte return address from {MBASE,SPS} into
PC[15:0]. The ending Program Counter is {MBASE,
PC[15:0]}.
}
1 .L The MADL control bit must be set to 1 to enable mixed-
ADL mode interrupts. The starting Program Counter is
PC[23:0]. Pop a byte from S2L into ADL to set the new
memory mode (03h = ADL, 02h = Z80).
If ADL mode {
Pop 3-byte return address from SPL into PC[23:0].
The ending Program Counter is PC[23:0]
}
else Z80 mode {
Pop a 2-byte return address from SPL into PC[15:0].
The ending Program Counter is {MBASE, PC[15:0]}.
}
Mnemonic Operand
ADL

Mode Cycle Opcode (hex)
RETI
— 0/1 6/7
ED, 4D
Table 86. RET Instruction Detail
ADL Suffix Operation