Inirx, Operation, Description – Zilog EZ80F916 User Manual
Page 187: Condition bits affected attributes
eZ80
®
CPU
User Manual
UM007715-0415
CPU Instruction Set
178
INIRX
Input from I/O and Increment Memory Address with Stationary I/O Address
Operation
repeat {
(HL) ({UU, DE[15:0]})
BC BC – 1
HL HL + 1
} while BC 0
Description
The CPU places the contents of register DE onto the lower byte of the address bus,
ADDR[15:0]. The upper byte of the address bus, ADDR[23:16], is undefined for I/O
addresses. The CPU reads the byte at this I/O address, {UU, DE[15:0]}, into CPU mem-
ory. The CPU next places the contents of HL onto the address bus and writes the byte to
the memory address specified by the HL register. The BC register decrements. The HL
register increments. Next, the CPU sets the Z Flag to 1 if the BC register decrements to 0.
The instruction repeats until the BC register equals 0.
Condition Bits Affected
Attributes
This instruction is not supported on eZ80190 device.
S
Not affected.
Z
Set of BC – 1 = 0; reset otherwise.
H
Not affected.
P/V
Not affected.
N
Set if Bit 7 of data = 1; reset otherwise.
C
Not affected.
Mnemonic Operand
ADL Mode Cycle
Opcode (hex)
INIRX
—
X
2
+
3
*
BC
ED, C2
INIRX.S
—
1
3
+
3
*
BC
52, ED, C2
INIRX.L
—
0
3
+
3
*
BC
49, ED, C2
Note: