Ld a, i, Operation, Description – Zilog EZ80F916 User Manual
Page 198: Condition bits affected attributes
eZ80
®
CPU
User Manual
UM007715-0415
CPU Instruction Set
189
LD A, I
Load Accumulator
Operation
A I[7:0]
Description
The CPU writes the contents of the lower byte of the Interrupt Vector register, I[7:0], to
the accumulator, A.
Condition Bits Affected
Attributes
S
Set if the I register is negative; reset otherwise.
Z
Set if the I register is 0; reset otherwise.
H
Reset.
P/V
Contains contents of IEF2.
N
Reset.
C
Not affected.
Mnemonic Operand
ADL Mode Cycle
Opcode (hex)
LD
A, I
X
2
ED, 57
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