Zilog EZ80F916 - Manual (Page 254)

eZ80
®
CPU
User Manual
UM007715-0415 CPU Instruction Set
245
LEA rr, IY+d
Load Effective Address
Operation
rr
 IY+d
Description
The rr operand is any of the multibyte CPU registers BC, DE, or HL. The CPU adds the
contents of the IY register to the signed displacement d and writes the sum to the multi-
byte rr register.
Condition Bits Affected
None.
Attributes
kk
identifies either the BC, DE, or HL multibyte register and is assembled into one of the
opcodes indicated in Table 74 .
Mnemonic Operand ADL Mode Cycle Opcode (hex)
LEA rr
,IY+d X 3
ED, kk, dd
LEA.S rr
,IY+d 1 4
52, ED, kk, dd
LEA.L rr
,IY+d 0 4
49, ED, kk, dd
Table 74. Register and kk Opcodes for LEA rr, IY+d Instruction (hex)
Register kk
BC
03
DE
13
HL
23