Zilog EZ80F916 - Manual (Page 81)

eZ80
®
CPU
User Manual
UM007715-0415 CPU Instruction Set
72
OUTI2
({00h, BC[15:0]})  (HL)
B  B – 1
C  C+1
HL  HL+1
ED A4
— * — — * —
PEA
IX+d
if ADL mode {
(SPL)  IX+d
SPL  SPL – 3
} 
else Z80 mode {
SPS  IX+d
SPS  SPS – 2
}
ED 65
— — — — — —
PEA
IY+d
if ADL mode {
(SPL)  IY+d
SPL  SPL – 3
}
else Z80 mode {
SPS  IY+d
SPS  SPS – 2
}
ED 66
— — — — — —
POP
ss
if ADL mode{
ss
 (SPL)
SPL  SPL+3
}
else Z80 mode {
ss
 {MBASE, SPS}
SPS  SPS+2
}
AF
F1
F  (SPL) or (SPS)
IX/Y DD/FD E1
— — — — — —
rr C1-E1
— — — — — —
Table 37. Instruction Summary (Continued)
Instruction and Operation
Address Mode
Opcode(s)
(Hex)
Flags Affected
Dest Source S Z H P/V N C
Note: *This flag value is a function of the result of the affected operation.
— = No Change.
0 = Set to 0.
1 = Set to 1.
V = Set to 1 if overflow occurs.
X = Undetermined.
P = Set to the parity of the result (0 if odd parity, 1 if even parity).
IEF2 = The value of Interrupt Enable Flag 2.