Zilog EZ80F916 - Manual (Page 223)

eZ80
®
CPU
User Manual
UM007715-0415 CPU Instruction Set
214
LD (IX/Y+d), rr
Load Indirect with Offset
Operation
(IX/Y+d)  rr
Description
The rr operand is any of the multibyte registers BC, DE, or HL. The CPU writes the con-
tents of the multibyte rr register to the memory location specified by the contents of the
multibyte Index Register, IX or IY, offset by the two’s-complement displacement d.
Condition Bits Affected
None.
Attributes
Mnemonic Operand ADL Mode Cycle Opcode (hex)
LD
(IX+d),BC 0/1 5/6
DD, 0F, dd
LD.S
(IX+d),BC 1 6
52, DD, 0F, dd
LD.L
(IX+d),BC 0 7
49, DD, 0F, dd
LD
(IX+d),DE 0/1 5/6
DD, 1F, dd
LD.S
(IX+d),DE 1 6
52, DD, 1F, dd
LD.L
(IX+d),DE 0 7
49, DD, 1F, dd
LD
(IX+d),HL 0/1 5/6
DD, 2F, dd
LD.S
(IX+d),HL 1 6
52, DD, 2F, dd
LD.L
(IX+d),HL 0 7
49, DD, 2F, dd
LD
(IY+d),BC 0/1 5/6
FD, 0F, dd
LD.S
(IY+d),BC 1 6
52, FD, 0F, dd
LD.L
(IY+d),BC 0 7
49, FD, 0F, dd
LD
(IY+d),DE 0/1 5/6
FD, 1F, dd
LD.S
(IY+d),DE 1 6
52, FD, 1F, dd
LD.L
(IY+d),DE 0 7 49, FD, 1F, dd
LD
(IY+d),HL 0/1 5/6 FD, 2F, dd
LD.S
(IY+d),HL 1 6 52, FD, 2F, dd
LD.L
(IY+d),HL 0 7 49, FD, 2F, dd