Zilog EZ80F916 - Manual (Page 255)

eZ80
®
CPU
User Manual
UM007715-0415 CPU Instruction Set
246
MLT rr
Multiply Register
Operation
rr
[15:0]  rr[15:8] x rr[7:0]
Description
The rr operand is any of the multibyte CPU registers BC, DE, or HL. The MLT instruc-
tion performs an 8-bit by 8-bit multiply operation. The rr operand Low byte is multiplied
by the rr operand High byte. The 16-bit product is written back into the 16-bit rr register
pair. The MLT instruction performs an 8-bit by 8-bit multiply operation with a 16-bit
result, regardless of the ADL mode.
Condition Bits Affected
None.
Attributes
Mnemonic Operand ADL Mode Cycle Opcode (hex)
MLT
BC X 6
ED 4C
MLT
DE X 6
ED 5C
MLT
HL X 6
ED 6C