Zilog EZ80F916 - Manual (Page 47)

eZ80
®
CPU
User Manual
UM007715-0415 Interrupts
38
eZ80
®
CPU Response to a Maskable Interrupt
The eZ80 ® CPU is capable of responding to a maskable interrupt using one of three inter-
rupt modes: Interrupt Mode 0, Interrupt Mode 1, or Interrupt Mode 2. The maskable inter-
rupt mode is set by the IM 0, IM 1, and IM 2 instructions. Not all products within the
eZ80 ® family support all 3 of these interrupt modes. Refer to the eZ80 ®
and
eZ80Acclaim!
®
product specifications
for information on supported interrupt modes.
Interrupt Mode 0
In Interrupt Mode 0, the interrupting device places the appropriate instruction onto the
data bus during the interrupt acknowledge cycle. Interrupt Mode 0 is the default state upon
reset of the CPU. Interrupt Mode 0 is also selected by execution of the IM 0 instruction.
The instruction placed on the data bus must be a single byte restart instruction, RST n,
with binary value
C7h
,
CFh
,
D7h
,
DFh
,
E7h
,
EFh
,
F7h
, or
FFh
, or a CALL Mmn instruc-
tion with binary value
CDh
. If any other binary value is placed on the data bus during the
interrupt acknowledge cycle, the CPU treats the instruction as a NOP. The binary opcodes
corresponding to the memory mode suffixes (.SIS, .LIL, .SIL, or .LIS) cannot be placed
on the data bus by the interrupting peripheral.
ADL mode 1 1
IEF2
 IEF1
IEF1
 0
The starting program counter is PC[23:0]. Push the 3-
byte return address, PC[23:0], onto the SPL stack.
Push a 03h byte onto the SPL stack, indicating an
interrupt from ADL mode (because ADL = 1). The ADL
mode bit remains set to 1. Write 000066h to PC[23:0].
The ending program counter is PC[23:0] = 000066h.
The interrupt service routine must end with RETN.L.
Table 21. Nonmaskable Interrupt Operation (Continued)
Current
Memory Mode
ADL
Mode
Bit MADL
Control
Bit
Operation