Zilog EZ80F916 - Manual (Page 75)

eZ80
®
CPU
User Manual
UM007715-0415 CPU Instruction Set
66
JR
cc’,d
if cc’ {PC  PC+d}
20–38
— — — — — —
JR
d
PC  PC+d
18
— — — — — —
LD
A,s
A  s
I[7:0]
ED 57
* * 0 IEF2 0 —
(IX/Y+d) DD/FD 7E — — — — — —
MB
ED 6E
— — — — — —
(Mmn) 3A
— — — — — —
R
ED 5F
* * 0 IEF2 0 —
(rr) 0A, 1A, 7E
— — — — — —
LD
HL,I
HL  I
ED D7
— — — — — —
LD
(HL),ss
(HL)  ss
IX/Y ED 3E-3F
— — — — — —
n 36
r 70-77
rr ED 0F-2F
LD
I,A
I[7:0]  A
ED 47
— — — — — —
LD
I,HL
I  HL
ED C7
— — — — — —
LD
ir, s
ir
 s
ir’ DD/FD 64-6D
— — — — — —
n DD/FD 26-2E
r DD/FD 60-67
LD
IX/Y, ss
IX/Y
 ss
(HL)
ED 31-7
— — — — — —
(IX/Y+d) DD/FD 31-37
Mmn DD/FD 21
(Mmn) DD/FD 2A
Table 37. Instruction Summary (Continued)
Instruction and Operation
Address Mode
Opcode(s)
(Hex)
Flags Affected
Dest Source S Z H P/V N C
Note: *This flag value is a function of the result of the affected operation.
— = No Change.
0 = Set to 0.
1 = Set to 1.
V = Set to 1 if overflow occurs.
X = Undetermined.
P = Set to the parity of the result (0 if odd parity, 1 if even parity).
IEF2 = The value of Interrupt Enable Flag 2.