Zilog EZ80F916 User Manual
Page 32
eZ80
®
CPU
User Manual
UM007715-0415
Memory Mode Switching
23
;already operating in Z80 Mode.
;The .IL portion of the suffix has
;no effect since instruction
;length is unambiguous.
LD.LIS (HL), BC
;24-bit value stored in BC[23:0]
;is written to the 24-bit memory
;location given by HL[23:0]. The
;.L portion of the suffix forces
;the use of 24-bit registers and
;24-bit addresses without
;MBASE.
;The .IS portion of the suffix has
;no effect since instruction
;length is unambiguous.
Suffix Example 5: LD (HL), BC in ADL Mode
.ASSUME ADL = 1
;ADL Mode operation is default.
LD (HL), BC
;24-bit value stored in BC[23:0]
;is written to the 24-bit memory
;location given by HL[23:0].
LD.SIS (HL), BC
;16-bit value stored in BC[15:0]
;is written to the 24-bit memory
;location given by
;{MBASE,HL[15:0]}. The .S portion
;of the suffix forces the use of
;16-bit values from the registers
;and uses MBASE with the address.
;The .IS portion of the suffix has
;no effect since instruction
;length is unambiguous.
LD.LIL (HL), BC
;24-bit value stored in BC[23:0]
;is written to the 24-bit memory
;location given by HL[23:0].
;Since operating in ADL mode, the
;.L suffix has no effect on this
;instruction execution.
;The .IL portion of the suffix has
;no effect since instruction
;length is unambiguous.
LD.SIL (HL), BC
;16-bit value stored in BC[15:0]
;is written to the 24-bit memory
;location provided by
;{MBASE,HL[15:0]}. The .S
;portion of the suffix forces the
;use of 16-bit registers and MBASE
;with the address.
;The .IL portion of the suffix has