Zilog EZ80F916 - Manual (Page 103)

eZ80
®
CPU
User Manual
UM007715-0415 CPU Instruction Set
94
ADD HL, rr
ADD without Carry
Operation
HL  HL+rr
Description
The rr operand is any of the multibyte registers BC, DE, or HL. The CPU adds the con-
tents of the rr register to the contents of the HL register, and stores the results in the HL
register.
Condition Bits Affected
Attributes
kk
identifies the BC, DE, or HL register and is assembled into one of the opcodes in
Table 41 .
S
Not affected.
Z
Not affected.
H
Set if carry from bit 11; reset otherwise.
P/V
Not affected.
N
Reset.
C
Set if carry from MSB; reset otherwise.
Mnemonic Operand ADL Mode Cycle Opcode (hex)
ADD
HL,rr X 1
kk
ADD.S
HL,rr 1 2
52, kk
ADD
.L HL,rr 0 2
49, kk