Zilog EZ80F916 - Manual (Page 14)

eZ80
®
CPU
User Manual
UM007715-0415 Architectural Overview
5
Figure 3. Pipeline Example
Clock
Address
Note: F & D = Fetch & Decode
Data In
Command
Execution
State
INC A Fetch Decode
Prefetch
Execute
F & D F & D Decode
Next command
1 clock delay for execution
Prefetch
Execute LD ( 1234h ), A
LD ( 5678h ), A
INC A
Data Out
INST_READ
MEM_READ
MEM_WRITE
PC
INC A LD (nn), A nL nH LD (nn), A Write nL nH INC A Write
PC+1 PC+2 PC+3 PC+4 PC+5 PC+6 PC+7
5678h 1234h
78h (1234h) 32h 12h (5678h) 3Ch 56h 34h 32h 3Ch
F & D F & D Decode
Prefetch
Execute
Valid Invalid Valid Invalid
Next command
1 clock delay for execution