Zilog EZ80F916 - Manual (Page 122)

eZ80
®
CPU
User Manual
UM007715-0415 CPU Instruction Set
113
Condition Bits Affected
None.
Attributes
The opcode (
kk
) depends on the condition code being tested. According to the relevant
condition code, the opcode is assembled as indicated in Table 48 .
1
.IS
The starting Program Counter is PC[23:0]. Push the 2
LS bytes of the return address, PC[15:0], onto the
{MBASE, SPS} stack. Push the MS byte of the return
address, PC[23:16], onto the SPL stack. Push a 03h
byte onto the SPL stack, indicating a call from ADL
mode (because ADL = 1). Reset ADL mode bit to 0.
Load a 2-byte logical address {mm, nn} from the
instruction into PC[15:0]. The ending Program Counter
is {MBASE, PC[15:0]} = {MBASE, mm, nn}.
0
.IL
The starting Program Counter is {MBASE, PC[15:0]}.
Push the 2-byte logical return address, PC[15:0], onto
the SPL stack. Push a 02h byte onto the SPL stack,
indicating a call from Z80 mode (because ADL = 0). Set
the ADL mode bit to 1. Load the 3-byte address {MM,
mm, nn} from the instruction into PC[23:0]. The ending
Program Counter is PC[23:0] = {MM, mm, nn}.
1
.IL
The starting Program Counter is PC[23:0]} Push the 3-
byte return address, PC[23:0], onto the SPL stack. Push
a 03h byte onto the SPL stack, indicating a call from
ADL mode (because ADL = 1 ). The ADL mode bit
remains set to 1. Load a 3-byte address {MM, mm, nn}
from the instruction into PC[23:0]. The ending Program
Counter is PC[23:0] = {MM, mm, nn}.
Mnemonic Operand ADL Mode Cycle Opcode (hex)
CALL cc
,mn 0 3/6
kk, nn, mm
CALL cc
,Mmn 1 4/7
kk, nn, mm, MM
CALL.IS cc
,mn 0 4/7
40, kk, nn, mm
CALL.IS cc
,mn 1 4/8
49, kk, nn, mm
CALL.IL cc
,Mmn 0 5/8
52, kk, nn, mm, MM
CALL.IL cc
,Mmn 1 5/9
5B, kk, nn, mm, MM
Table 47. Conditional Operations for CALL cc, Mmn Instruction (Continued)