Zilog EZ80F916 - Manual (Page 196)

eZ80
®
CPU
User Manual
UM007715-0415 CPU Instruction Set
187
JR cc’, d
Conditional Jump Relative
Operation
if cc’ {
PC  PC+d
}
Description
If the condition cc’ (NZ, Z, NC or C) is true (a logical 1), then the two’s-complement dis-
placement d is added to the Program Counter. The jump is measured from the address of
the byte following the instruction.
Condition Bits Affected
None.
Attributes
The opcode
kk
depends on the condition code being tested. According to the relevant con-
dition code, the opcode is assembled as indicated in Table 62 .
Mnemonic Operand ADL Mode Cycle Opcode (hex)
JR cc’
,d X 2/3
kk, dd
Table 62. Opcode Assembly for JR cc’, d Instruction
Condition Relevant Flag Opcode (hex)
NZ
(non 0) Z
20
Z
(0) Z
28
NC
(no carry) C
30
C (carry) C
38