Zilog EZ80F916 - Manual (Page 167)

eZ80
®
CPU
User Manual
UM007715-0415 CPU Instruction Set
158
INC (IX/Y+d)
Increment
Operation
(IX/Y+d)  (IX/Y+d)+1
Description
The (IX/Y+d) operand is an 8-bit register at the memory location specified by the contents
of the Index Register, IX or IY, added to the two’s-complement displacement d. The CPU
increments the contents of this 8-bit register by 1.
Condition Bits Affected
Attributes
S
Set if result is negative; reset otherwise.
Z
Set if result is 0; reset otherwise.
H
Set if carry from bit 3.
P/V
Set if operand was 7Fh before operation.
N
Reset.
C
Not affected.
Mnemonic Operand ADL Mode Cycle Opcode (hex)
INC
(IX+d) X 6
DD, 34, dd
INC.S
(IX+d) 1 7
52, DD, 34, dd
INC
.L (IX+d) 0 7
49, DD, 34, dd
INC
(IY+d) X 6
FD, 34, dd
INC.S
(IY+d) 1 7
52, FD, 34, dd
INC
.L (IY+d) 0 7
49, FD, 34, dd