Zilog EZ80F916 - Manual (Page 374)

eZ80
®
CPU
User Manual
UM007715-0415 CPU Instruction Set
365
TST A, r
Test
Operation
A AND r
Description
The r operand is any of the 8-bit CPU registers A, B, C, D, E, H, or L. The r operand is
bitwise ANDed with the contents of the accumulator, A. The appropriate flags are set to 1,
depending on the result of the AND logical operation. The contents of the accumulator
and the r operand are not altered.
Condition Bits Affected
Attributes
jj
identifies the A, B, C, D, E, H, or L register and is assembled into one of the opcodes
indicated in Table 103 .
S
Set if result is negative; reset otherwise.
Z
Set if result is 0; reset otherwise.
H
Set.
P/V
Set if parity is even; reset otherwise.
N
Reset.
C
Reset
Mnemonic Operand ADL Mode Cycle Opcode (hex)
TST
A,r X 2
ED, jj