Otdr, Operation, Description – Zilog EZ80F916 User Manual
Page 269: Condition bits affected attributes
eZ80
®
CPU
User Manual
UM007715-0415
CPU Instruction Set
260
OTDR
Output to I/O and Decrement
Operation
repeat {
({UU, BC[15:0]}) (HL)
B B – 1
HL HL – 1
} while B 0
Description
The CPU loads the contents of the memory location specified by the multibyte HL register
into CPU memory. The CPU next outputs this byte to I/O address {UU, BC[15:0]}. The
upper byte of the address bus, ADDR[23:16] is undefined for I/O addresses. The B and
HL registers are decremented. The instruction repeats until register B equals 0.
Condition Bits Affected
Attributes
S
Not affected.
Z
Set if B – 1 = 0; reset otherwise.
H
Not affected.
P/V
Not affected.
N
Set if msb of data is logical 1; reset otherwise.
C
Not affected.
Mnemonic Operand
ADL Mode Cycle
Opcode (hex)
OTDR
—
X
2
+
3
*
B
ED, BB
OTDR.S
—
1
3
+
3
*
B
52, ED, BB
OTDR.L
—
0
3
+
3
*
B
49, ED, BB