Operation, Description, Condition bits affected attributes – Zilog EZ80F916 User Manual
Page 180
eZ80
®
CPU
User Manual
UM007715-0415
CPU Instruction Set
171
INI
Input from I/O and Increment
Operation
(HL) ({UU, BC[15:0]})
B B – 1
HL HL+1
Description
The CPU places the contents of BC[15:0] onto the lower two bytes of the address bus,
ADDR[15:0]. The upper byte of the address bus, ADDR[23:16] is undefined for I/O
addresses. The CPU reads the byte located at I/O address {UU, BC[15:0]} into CPU mem-
ory. The CPU next places the contents of HL onto the address bus and writes the byte to
the memory address specified by the HL register. The B register decrements and the HL
register increments. Next, the CPU sets the Z Flag to 1 if the B register decrements to 0.
Condition Bits Affected
Attributes
S
Not affected.
Z
Set if B – 1 = 0; reset otherwise.
H
Not affected.
P/V
Not affected.
N
Set if msb of data is a logical 1; reset otherwise.
C
Not affected.
Mnemonic Operand
ADL Mode Cycle
Opcode (hex)
INI
—
X
5
ED, A2
INI.S
—
1
6
52, ED, A2
INI.L
—
0
6
49, ED, A2