Zilog EZ80F916 - Manual (Page 74)

eZ80
®
CPU
User Manual
UM007715-0415 CPU Instruction Set
65
INIMR
repeat {
(HL)  ({0000h, C})
B  B – 1
C  C+1
HL  HL+1
} while B  0
ED 92
— 1 — — * —
INIR
repeat {
(HL)  ({00h, BC[15:0]})
B  B – 1
HL  HL+1
} while B  0
ED B2
— 1 — — * —
INIRX
repeat {
(HL)  ({00h, DE[15:0]})
BC  BC – 1
HL  HL + 1
} while BC  0
ED C2
— 1 — — * —
JP
cc,Mmn
if cc {
PC  Mmn {
if .S {ADL  0}
else if .L {ADL  1}
}
C2-FA
— — — — — —
JP
(ss)
PC  ss
if .S {ADL  0}
else if .L {ADL  1}
(HL)
E9
— — — — — —
(IX/Y) DD/FD E9
JP
Mmn
PC  Mmn {
if .S {ADL  0}
else if .L {ADL  1}
C3
— — — — — —
Table 37. Instruction Summary (Continued)
Instruction and Operation
Address Mode
Opcode(s)
(Hex)
Flags Affected
Dest Source S Z H P/V N C
Note: *This flag value is a function of the result of the affected operation.
— = No Change.
0 = Set to 0.
1 = Set to 1.
V = Set to 1 if overflow occurs.
X = Undetermined.
P = Set to the parity of the result (0 if odd parity, 1 if even parity).
IEF2 = The value of Interrupt Enable Flag 2.