Zilog EZ80F916 - Manual (Page 209)

eZ80
®
CPU
User Manual
UM007715-0415 CPU Instruction Set
200
LD I, HL
Load Interrupt Vector
Operation
I  HL
Description
The CPU writes the contents of the accumulator, HL, to the 16-bit Interrupt Vector regis-
ter, I.
Condition Bits Affected
None.
Attributes
This instruction is not supported on eZ80190, eZ80L92, or eZ80F92/F93 devices.
Mnemonic Operand ADL Mode Cycle Opcode (hex)
LD
I,HL X 2
ED, C7
Note: