Ld a, (rr), Operation, Description – Zilog EZ80F916 User Manual
Page 203: Condition bits affected, Attributes
eZ80
®
CPU
User Manual
UM007715-0415
CPU Instruction Set
194
LD A, (rr)
Load Accumulator
Operation
A (rr)
Description
The rr operand is any of BC, DE, or HL. The CPU writes the contents of the memory
location specified by the multibyte register to the accumulator, A.
Condition Bits Affected
None.
Attributes
Mnemonic
Operand
ADL Mode
Cycle
Opcode (hex)
LD
A,(BC)
X
2
0A
LD.S
A,(BC)
1
3
52, 0A
LD.L
A,(BC)
0
3
49, 0A
LD
A,(DE)
X
2
1A
LD.S
A,(DE)
1
3
52, 1A
LD.L
A,(DE)
0
3
49, 1A
LD
A,(HL)
X
2
7E
LD.S
A,(HL)
1
3
52, 7E
LD.L
A,(HL)
0
3
40, 7E
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