Zilog EZ80F916 - Manual (Page 358)

eZ80
®
CPU
User Manual
UM007715-0415 CPU Instruction Set
349
SRA (IX/Y+d)
Shift Right Arithmetic
Operation
Description
The (IX/Y+d) operand is an 8-bit value at the memory location specified by the contents
of the Index Register, IX or IY, added to the two’s-complement displacement d. The CPU
manipulates the contents of this memory location, (IX/Y+d), by shifting them right one bit
position. The CPU next copies the contents of bit 0 into the Carry Flag and leaves the pre-
vious contents of bit 7 unchanged.
Condition Bits Affected
Attributes
S
Set if result is negative; reset otherwise.
Z
Set if result is 0; reset otherwise.
H
Reset.
P/V
Set if parity is even; reset otherwise.
N
Reset.
C
Data from bit 0 of the source.
Mnemonic Operand ADL Mode Cycle Opcode (hex)
SRA
(IX+d) X 7
DD, CB, dd, 2E
SRA.S
(IX+d) 1 8
52, DD, CB, dd, 2E
SRA.L
(IX+d) 0 8
49, DD, CB, dd, 2E
SRA
(IY+d) X 7
FD, CB, dd, 2E
SRA.S
(IY+d) 1 8
52, FD, CB, dd, 2E
SRA.L
(IY+d) 0 8
49, FD, CB, dd, 2E
C 7 0
(IX/Y+d)