Zilog EZ80F916 - Manual (Page 396)

eZ80
®
CPU
User Manual
UM007715-0415 Glossary
387
IND.
Input from I/O and Decrement; an input/output instruction.
Index registers (IX and IY).
The multibyte registers IX and IY allow standard addressing and relative
displacement addressing in memory.
INDM.
Input from I/O and Decrement; an input/output instruction.
INDMR.
Input from I/O and Decrement with Repeat; an input/output instruction.
INDR.
Input from I/O and Decrement with Repeat; an input/output instruction.
IND2.
Input from I/O and Decrement; an input/output instruction.
IND2R.
Input from I/O and Decrement with Repeat; an input/output instruction.
INI.
Input from I/O and Increment; an input/output instruction.
INIM.
Input from I/O and Increment; an input/output instruction.
INIMR.
Input from I/O and Increment with Repeat; an input/output instruction.
INIR.
Input from I/O and Increment with Repeat; an input/output instruction.
INI2.
Input from I/O and Increment; an input/output instruction.
INI2R.
Input from I/O and Increment with Repeat; an input/output instruction.
INT.
Interrupt.
INTACK.
Interrupt Acknowledge.
Internet Control Message Protocol.
An Internet protocol that reports datagram delivery errors. ICMP is
a key part of the TCP/IP protocol suite. The packet internet gopher (ping) application is based on ICMP.
Internet protocol (IP).
A DOD standard protocol designed for use in interconnected systems of packet-
switched computer communication networks.
interrupt.
A suspension of a process, such as the execution of a computer program, caused by an event
external to that process, and performed in such a way that the process can be resumed. The three types of
interrupts include: internal hardware, external hardware, and software.
interrupt acknowledge cycle.
The time required for the eZ80 ® CPU to respond to an interrupt service
request.
Interrupt Enable Flag.
In the eZ80
®
CPU, there are two interrupt enable flags, IEF1 and IEF2, that are set
or reset using the Enable Interrupt (EI) and Disable Interrupt (DI) instructions.
Interrupt Page Address register (I).
The 8-bit I register stores the upper 8 bits of the interrupt vector
table address for Mode 2 vectored interrupts.
interrupt request (IRQ).
Hardware lines that carry a signal from a device to the processor.
Interrupt Service Routine.
An interrupt service routine can affect the exchange of data, status
information, or control information between the CPU and an interrupting peripheral.
interrupt vector address.
The address used by the eZ80
®
CPU as the starting point for the associated
interrupt service routine.
IN0.
Input from I/O on Page 0; an input/output instruction.
IOCS.
Auxiliary Chip Select Output Signal.
IORQ.
I/O Request.
IP.
Internet Protocol.