Zilog EZ80F916 - Manual (Page 80)

eZ80
®
CPU
User Manual
UM007715-0415 CPU Instruction Set
71
OTIR
repeat {
({00h, BC[15:0]})  (HL)
B  B – 1
HL  HL+1
} while B  0
ED B3
— 1 — — * —
OTIRX
repeat {
({00h, DE[15:0]})  (HL)
BC  BC – 1
HL  HL + 1
} while BC  0
ED C3
— 1 — — * —
OUT
(BC),r also OUT (C),r
({00h, BC[15:0]})  r
ED 41–79
— — — — — —
OUT
(n),A
({00h, A, n})  A
D3
— — — — — —
OUT0
(n),r
({0000h, n})  r
ED 01–39
— — — — — —
OUTD
({00h, BC[15:0]})  (HL)
B  B – 1
HL  HL – 1
ED AB
— * — — * —
OUTD2
({00h, BC[15:0]})  (HL)
B  B – 1
C  C – 1
HL  HL – 1
ED AC
— * — — * —
OUTI
({00h, BC[15:0]})  (HL)
B  B – 1
HL  HL+1
ED A3
— * — — * —
Table 37. Instruction Summary (Continued)
Instruction and Operation
Address Mode
Opcode(s)
(Hex)
Flags Affected
Dest Source S Z H P/V N C
Note: *This flag value is a function of the result of the affected operation.
— = No Change.
0 = Set to 0.
1 = Set to 1.
V = Set to 1 if overflow occurs.
X = Undetermined.
P = Set to the parity of the result (0 if odd parity, 1 if even parity).
IEF2 = The value of Interrupt Enable Flag 2.