Zilog EZ80F916 - Manual (Page 77)

eZ80
®
CPU
User Manual
UM007715-0415 CPU Instruction Set
68
LDD
(DE)  (HL)
DE  DE – 1
HL  HL – 1
BC  BC – 1
ED A8
— — 0 * 0 —
LDDR
repeat {
(DE)  (HL)
DE  DE – 1
HL  HL – 1
BC  BC – 1
} while BC  0
ED B8
— — 0 * 0 —
LDI
(DE)  (HL)
DE  DE+1
HL  HL+1
BC  BC – 1
ED A0
— — 0 * 0 —
LDIR
repeat {
(DE)  (HL)
DE  DE+1
HL  HL+1
BC  BC – 1
} while BC  0
ED B0
— — 0 * 0 —
LEA
IX/Y, IX+d
IX/Y
 IX+d
IX+d
ED 32-55
— — — — — —
LEA
IX/Y, IY+d
IX/Y
 IY+d
IY+d
ED 33-54
— — — — — —
LEA
rr, IX+d
rr
 IX+d
IX+d
ED 02-22
— — — — — —
LEA
rr, IY+d
rr
 IY+d
IY+d
ED 03-23
— — — — — —
Table 37. Instruction Summary (Continued)
Instruction and Operation
Address Mode
Opcode(s)
(Hex)
Flags Affected
Dest Source S Z H P/V N C
Note: *This flag value is a function of the result of the affected operation.
— = No Change.
0 = Set to 0.
1 = Set to 1.
V = Set to 1 if overflow occurs.
X = Undetermined.
P = Set to the parity of the result (0 if odd parity, 1 if even parity).
IEF2 = The value of Interrupt Enable Flag 2.