Zilog EZ80F916 - Manual (Page 204)

eZ80
®
CPU
User Manual
UM007715-0415 CPU Instruction Set
195
LD HL, I
Load Register
Operation
HL  I
Description
The CPU writes the contents of the 16-bit Interrupt Vector register, I, to the multibyte reg-
ister, HL.
Condition Bits Affected
Attributes
Note
This instruction is not supported on eZ80190, eZ80L92, or eZ80F92/F93 devices.
S
Set if the I register is negative; reset otherwise.
Z
Set if the I register is 0; reset otherwise.
H
Reset.
P/V
Contains contents of IEF2.
N
Reset.
C
Not affected.
Mnemonic Operand ADL Mode Cycle Opcode (hex)
LD
HL, I X 2
ED, D7