Zilog EZ80F916 - Manual (Page 31)

eZ80
®
CPU
User Manual
UM007715-0415 Memory Mode Switching
22
LD.SIL HL, 123456h ;HL[23:0]
{00h, 3456h}.
;.IL directs eZ80 to fetch 24 bits
;of data. .S forces upper byte of
;HL register to an undefined
;state. A different value is
;stored in HL than expected.
LD.SIL (123456h), HL;(3456h)
HL.
;.IL forces a fetch of a 24-bit
;indirect address. .S forces Z80
;mode for writes to memory, thus
;address of write is {MBASE,
;3456h} rather than the address
;123456h that may be expected.
Suffix Example 4: LD (HL), BC in Z80 Mode
The following two examples, Suffix Example 4 and Suffix Example 5, further demon-
strate how the suffixes affect internal CPU register operation and the creation of addresses.
In these two suffix examples, the .IS and .IL portions of the suffix have no effect because
the length of this instruction is unambiguous.
.ASSUME ADL = 0 ;Z80 Mode operation is default.
LD (HL), BC ;16-bit value stored in BC[15:0]

;is written to the 24-bit memory

;location given by

;{MBASE, HL[15:0]}.
LD.SIS (HL), BC ;16-bit value stored in BC[15:0]

;is written to the 24-bit memory

;location given by

;{MBASE, HL[15:0]}. The .S portion

;of the suffix has no effect since

;already operating in Z80 Mode.

;The .IS portion of the suffix has

;no effect since instruction

;length is unambiguous.
LD.LIL (HL), BC ;24-bit value stored in BC[23:0]

;is written to the 24-bit memory

;location given by HL[23:0]. The

;.L portion of the suffix forces

;the use of 24-bit registers and

;24-bit addresses without MBASE.

;The .IL portion of the suffix has

;no effect since instruction

;length is unambiguous.
LD.SIL (HL), BC ;16-bit value stored in BC[15:0]

;is written to the 24-bit memory

;location given by

;{MBASE,HL[15:0]}. The .S portion

;of the suffix has no effect since
