Otd2r, Operation, Description – Zilog EZ80F916 User Manual
Page 265
eZ80
®
CPU
User Manual
UM007715-0415
CPU Instruction Set
256
OTD2R
Output to I/O and Decrement with Repeat
Operation
repeat {
({UU, DE[15:0]}) (HL)
BC BC – 1
DE DE – 1
HL HL – 1
} while BC 0
Description
The CPU loads the contents of the memory location specified by the multibyte HL register
into CPU memory. This byte is output to I/O address {UU, DE[15:0]}. The upper byte of
the address bus, ADDR[23:16] is undefined for I/O addresses. The BC, DE, and HL regis-
ters are decremented. The instruction repeats until the BC register equals 0.
Condition Bits Affected
Attributes
Note
This instruction operates differently in eZ80190 device. In the eZ80190, operation is:
repeat {
({UU, BC[15:0]}) (HL)
B B – 1
S
Not affected.
Z
Set if B C– 1 = 0; reset otherwise.
H
Not affected.
P/V
Not affected.
N
Set if msb of data is logical 1; reset otherwise.
C
Not affected.
Mnemonic Operand
ADL Mode Cycle
Opcode (hex)
OTD2R
—
X
2
+
3
*
B
ED, BC
OTD2R.S
—
1
3
+
3
*
B
52, ED, BC
OTD2R.L
—
0
3
+
3
*
B
49, ED, BC