Pea ix+d, Operation, Description – Zilog EZ80F916 User Manual
Page 284: Condition bits affected, Attributes
eZ80
®
CPU
User Manual
UM007715-0415
CPU Instruction Set
275
PEA IX+d
Push Effective Address
Operation
if ADL mode{
(SPL – 1) IXd[23:16]
(SPL – 2) IXd[15:8]
(SPL – 3) IXd[7:0]
SPL SPL – 3
}
else Z80 mode {
(SPS – 1) IXd[15:8]
(SPS – 2) IXd[7:0]
SPS SPS – 2
}
where IXd indicates the sum of the contents of the register IX and the two’s-complement
displacement d
.
Description
In ADL mode, the 24-bit sum of the contents of IX and the two’s-complement displace-
ment d is pushed onto the stack at SPL. The stack pointer, SPL, decrements by 3.
In Z80 mode, the 16-bit sum of the contents of IX and the two’s-complement displacement
d
is pushed onto the stack at SPS. The stack pointer, SPS, decrements by 2.
Condition Bits Affected
None.
Attributes
Mnemonic Operand
ADL Mode Cycle
Opcode (hex)
PEA
IX+d
0/1
5/6
ED, 65, dd
PEA.S
IX+d
1
6
52, ED, 65, dd
PEA.L
IX+d
0
7
49, ED, 65, dd