Zilog EZ80F916 - Manual (Page 45)

eZ80
®
CPU
User Manual
UM007715-0415 Interrupts
36
Interrupts
Interrupts allow peripheral devices to suspend CPU operation in an orderly manner and
force the CPU to start an interrupt service routine (ISR). Usually this interrupt service rou-
tine is involved with the exchange of data, status information, or control information
between the CPU and the interrupting peripheral. When the service routine is completed,
the CPU returns to the operation from which it was interrupted.
The CPU respond to two different interrupt types—maskable interrupts and nonmaskable
interrupts. The nonmaskable interrupt (NMI) cannot be disabled by the programmer. An
NMI request is always accepted when the peripheral device requests it. You can enable or
disable maskable interrupts.
Interrupt Enable Flags (IEF1 and IEF2)
In the eZ80 ® CPU, there are two interrupt enable flags (IEF1 and IEF2) that are set or
reset using the Enable Interrupt (EI) and Disable Interrupt (DI) instructions. When IEF1 is
reset to 0 by a DI instruction, a maskable interrupt cannot be accepted by the CPU. When
IEF1 is set to 1 by an EI instruction, a maskable interrupt is acknowledged by the CPU
and executed.
The state of IEF1 is used to enable or inhibit interrupts, while IEF2 is used as a temporary
storage location for IEF1. At reset, the CPU clears both IEF1 and IEF2 to 0, which dis-
ables the maskable interrupts. The maskable interrupts can be enabled using the EI
instruction. No pending interrupt is accepted until the instruction that follows the EI
instruction is executed. The single instruction delay occurs because EI is often followed
by a return instruction, and because interrupts must not be allowed until the return is com-
plete.
When a maskable interrupt is accepted by the CPU, both IEF1 and IEF2 are reset to the
disabled state, thus inhibiting further interrupts until a new EI instruction is executed. For
all of the cases discussed previously in this section, IEF1 and IEF2 are always equal.
The purpose of IEF2 is to save the status of IEF1 when a nonmaskable interrupt occurs.
When a nonmaskable interrupt is accepted, IEF1 is reset to prevent further interrupts until
reenabled by the application code. The status of IEF1 is restored by executing the Return
From Nonmaskable (RETN) instruction. During execution of a Return From Nonmask-
able Interrupt, the CPU copies the contents of IEF2 back into IEF1. In addition, the LD
A,I
or LD A,R instructions copy the state of IEF2 into the Parity flag where it can be
tested or stored.
Interrupts in Mixed Memory Mode Applications
For all mixed-memory mode applications, the MADL control bit must be set to 1 using the
STMIX
instruction. When the MADL is set to 1, all interrupt service routines (ISRs)