Ld (mmn), ix/y, Operation, Description – Zilog EZ80F916 User Manual
Page 226: Condition bits affected, Attributes
eZ80
®
CPU
User Manual
UM007715-0415
CPU Instruction Set
217
LD (Mmn), IX/Y
Load Indirect
Operation
(Mmn)
IX/Y
Description
The CPU stores the contents of the multibyte Index Register, IX or IY, in the memory
location specified by 16- or 24-bit constant Mmn.
Condition Bits Affected
None
Attributes
Zilog recommends against using the .SIL and .LIS suffixes with this instruction. The .SIL
instruction fetches a 24-bit value, Mmn. However, this instruction ignores the upper byte
and uses address {MBASE, mm, nn} instead. The .LIS instruction fetches a 16-bit value,
mn. However, the .LIS instruction does not use the MBASE value. Instead, it uses address
{00, mm, nn}.
Mnemonic Operand
ADL
Mode
Cycle
Opcode (hex)
LD
(mn)
,IX
0
6
DD, 22, nn, mm
LD
(Mmn)
,IX 1
8
DD, 22, nn, mm, MM
LD.SIS
(mn)
,IX
1
7
40, DD, 22, nn, mm
LD.LIL
(Mmn)
,IX 0
9
5B, DD, 22, nn, mm, MM
LD
(mn)
,IY
0
6
FD, 22, nn, mm
LD
(Mmn)
,IY 1
8
FD, 22, nn, mm, MM
LD.SIS
(mn)
,IY
1
7
40, FD, 22, nn, mm
LD.LIL
(Mmn)
,IY 0
9
5B, FD, 22, nn, mm, MM
Note: