Dec rr, Operation, Description – Zilog EZ80F916 User Manual
Page 147: Condition bits affected, Attributes
eZ80
®
CPU
User Manual
UM007715-0415
CPU Instruction Set
138
DEC rr
Decrement
Operation
rr
rr – 1
Description
The rr operand is any of the multibyte CPU registers BC, DE, or HL. The value contained
in the specified register is decremented by 1.
Condition Bits Affected
None.
Attributes
kk
identifies the BC, DE, or HL register and is assembled into one of the opcodes indi-
cated in
Mnemonic
Operand
ADL Mode
Cycle
Opcode (hex)
DEC
rr
X
1
kk
DEC.S
rr
1
2
52, kk
DEC
.L
rr
0
2
49, kk
Table 53. Register and kk Opcodes for DEC rr Instruction (hex)
Register kk
BC
0B
DE
1B
HL
2B
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