Zilog EZ80F916 - Manual (Page 240)

eZ80
®
CPU
User Manual
UM007715-0415 CPU Instruction Set
231
LD rr, (Mmn)
Load Register
Operation
rr
 (Mmn)
Description
The rr operand is any of the multibyte CPU registers BC, DE, or HL. The 16- or 24-bit
operand (Mmn) specifies a location in memory. The 16- or 24-bit value stored at this loca-
tion in memory is written to the multibyte rr register.
Condition Bits Affected
None.
Attributes
kk
identifies the BC or DE register and is assembled into one of the opcodes indicated in
Table 72 .

Zilog recommends against using the .SIL and .LIS suffixes with this instruction. The .SIL
instruction fetches a 24-bit value, Mmn. However, this instruction ignores the upper byte
and uses address {MBASE, mm, nn} instead. The .LIS instruction fetches a 16-bit value,
mn. However, the .LIS instruction does not use the MBASE value. Instead, it uses address
{00, mm, nn}.
Mnemonic Operand
ADL
Mode
Cycle Opcode (hex)
LD rr
,(mn) 0 6
ED, kk, nn, mm
LD rr
,(Mmn) 1 8
ED, kk, nn, mm, MM
LD.LIL rr
,(Mmn) 0 9
5B, ED, kk, nn, mm, MM
LD.SIS rr
,(mn) 1 7
40, ED, kk, nn, mm
LD
HL, (mn) 0 5
2A, nn, mm
LD
HL, (Mmn) 1 7
2A, nn, mm, MM
LD.LIL
HL, (Mmn) 0 8
5B, 2A, nn, mm, MM
LD.SIS
HL, (mn) 1 6
40, 2A, nn, mm
Note: