Zilog EZ80F916 - Manual (Page 12)

eZ80
®
CPU
User Manual
UM007715-0415 Architectural Overview
3
and WRITEs. It also discards prefetched instructions when jumps, interrupts, and other
control transfer events occur.
Mode Control
The Mode Control block of the CPU controls which mode the processor is currently oper-
ating in: HALT mode, SLEEP mode, Interrupt mode, debug mode, and ADL mode 1 .
Opcode Decoder
The opcodes are decoded within the CPU control block. After each instruction is fetched,
it is passed to the decoder. The opcode decoder is organized similarly to a large micro-
coded ROM.
CPU Registers
The CPU registers are contained within the CPU’s data block. Some are special purpose
registers, such as the Program Counter, the Stack Pointer, and the Flags register. There are
also a number of CPU control registers.
ALU
The arithmetic logic unit (ALU) is contained within the CPU’s data block. The ALU per-
forms the arithmetic and logic functions on the addresses and the data passed over from
the control block or from the CPU 
registers.
Address Generator
The address generator creates the addresses for all CPU memory READ and WRITE oper-
ations. The address generator also contains the Z80 Memory Mode Base Address register
(MBASE) for address translation in Z80 mode operation.
Data Selector
The data selector places the appropriate data onto the data bus. The data selector controls
the data path based on the instruction currently being executed.
Pipeline Description
The CPU pipeline reduces the overall cycle time for each instruction. In principle, each
instruction must be fetched, decoded, and executed. This process normally spans at least
three cycles. The CPU pipeline, however, can reduce the overall time of some instructions
to as little as one cycle by allowing the next instruction to be prefetched and decoded
1. The debug interface is discussed in greater detail in the
eZ80
®
product specification and eZ80Acclaim!
®
product specification.