Zilog EZ80F916 - Manual (Page 395)

eZ80
®
CPU
User Manual
UM007715-0415 Glossary
386
EQ.
A Boolean operator meaning Equal to.
EX.
Exchange Registers; an exchange instruction.
EXX.
Exchange CPU Multibyte Register Banks; an exchange instruction.
exception.
An error, unusual condition, or external signal that can set a status bit. It may or may not cause
an interrupt, depending on whether or not the corresponding interrupt is enabled.
EXTAL.
External clock/crystal.
eZ80
®
.
Zilog’s next-generation Internet processor core. A single-cycle instruction fetch machine that is
four times faster than Zilog’s original Z80, offering linear addressing that can address up to 16 MB of
memory.
Fetch.
The act of retrieving information (instructions or data) from memory.
glitch.
A pulse or burst of noise; sometimes reserved for the more annoying types of noise pulses that
cause crashes and failures.
GPIO.
General Purpose Input/Output.
GPR.
General Purpose Register.
H.
See Half-Carry Flag.
h.
See Hexadecimal.
Half-Carry Flag.
The Half-Carry Flag is set or reset, depending on the carry and borrow status between
bits 3 and 4 of an 8-bit arithmetic operation. This flag is used by the decimal adjust accumulator instruction
(DAA) to correct the result of a packed BCD addition or subtraction.
HALT.
HALT mode; a processor control instruction.
high-pass filter.
A filter that passes frequencies above a given frequency and attenuates all others.
I
2
C.
The Inter-Integrated Circuit serial bus developed by Phillips International for interconnecting devices
within electronics, telecommunications, and industrial consumer electronic products.
ICE.
In-Circuit Emulator. A Zilog product that supports the application design process.
IE.
Interrupt Enable.
IEF1 and IEF2.
See Interrupt Enable Flag.
IEI.
Interrupt Enable IN.
IEO.
Interrupt Enable OUT.
IIHX.
Intel Hexadecimal format.
IllOp.
Illegal Operation.
IM.
Immediate Data Addressing Mode. Interrupt Mode; a processor control instruction. On the eZ80 ®
CPU, there are 3 interrupt mode instructions: IM 0, IM 1, and IM 2.
IMASK.
Interrupt mask register.
IMR.
Interrupt Mask Register.
IN.
Input from I/O; an input/output instruction.
INC.
Increment; an arithmetic instruction.
INCW.
Increment Word.