Zilog EZ80F916 - Manual (Page 46)

eZ80
®
CPU
User Manual
UM007715-0415 Interrupts
37
begin in ADL mode. To explain, the ADL mode bit is set to 1 and full 24-bit linear
addressing is used to access the ISRs. The ADL mode bit setting of the interrupted code is
pushed onto the stack, using SPL, to allow the memory mode to return to the appropriate
value after completion of the ISR. For mixed-memory mode applications, all ISRs must
end with either a RETI.L for maskable interrupts or RETN.L for nonmaskable interrupts.
eZ80
®
CPU Response to a Nonmaskable Interrupt
The CPU always accepts a nonmaskable interrupt (NMI). The state of the Interrupt Enable
flags (IEF1 and IEF2) have no effect on nonmaskable interrupt operation. CPU operation
in response to an NMI is described in detail in Table 21 .
Table 21. Nonmaskable Interrupt Operation
Current
Memory Mode
ADL
Mode
Bit MADL
Control
Bit
Operation
Z80 mode 0 0
IEF2
 IEF1
IEF1
 0
The starting program counter is {MBASE, PC[15:0]}.
Push the 2-byte return address, PC[15:0], onto the
{MBASE,SPS} stack. The ADL mode bit remains
cleared to 0. Write 0066h to PC[15:0]. The ending
program counter is {MBASE, PC[15:0]} = {MBASE,
0066h
}. The interrupt service routine must end with
RETN
.
ADL mode 1 0
IEF2
 IEF1
IEF1
 0
The starting program counter is PC[23:0]. Push the 3-
byte return address, PC[23:0], onto the SPL stack. The
ADL mode bit remains set to 1. Write 000066h to
PC[23:0]. The ending program counter is
PC[23:0] = 000066h. The interrupt service routine must
end with RETN.
Z80 mode 0 1
IEF2
 IEF1
IEF1
 0
The starting program counter is {MBASE, PC[15:0]}.
Push the 2-byte return address, PC[15:0], onto the
SPL stack. Push a 02h byte onto the SPL stack,
indicating interrupting from Z80 mode (because
ADL = 0). Set the ADL mode bit to 1. Write 000066h to
PC[23:0]. The ending program counter is
PC[23:0] = 000066h. The interrupt service routine must
end with RETN.L.