Zilog EZ80F916 - Manual (Page 110)

eZ80
®
CPU
User Manual
UM007715-0415 CPU Instruction Set
101
AND A, ir
Logical AND
Operation
A  A AND ir
Description
The ir operand is any of the 8-bit registers IXH, IXL, IYH, or IYL. The ir operand is bit-
wise ANDed with the contents of the accumulator, A. The result is stored in the accumula-
tor.
Condition Bits Affected
Attributes
S
Set if result is negative; reset otherwise.
Z
Set if result is 0; reset otherwise.
H
Set.
P/V
Set if parity is even; reset otherwise.
N
Reset.
C
Reset.
Mnemonic Operand ADL Mode Cycle Opcode (hex)
AND
A,IXH X 2
DD, A4
AND
A,IXL X 2
DD, A5
AND
A,IYH X 2
FD, A4
AND
A,IYL X 2
FD, A5